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| HV2701 Low Charge Injection 16-Channel High Voltage Analog Switch with Bleed Resistors Features HVCMOS technology for high performance Integrated bleed resistors on the outputs 16 Channels of high voltage analog switch 3.3V input logic level compatible 20MHz data shift clock frequency Very low quiescent power dissipation-10A Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages General Description The Supertex HV2701 is a low charge injection, 16-channel, high voltage, analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Applications Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Optical MEMS modules Block Diagram Latches D LE CL Level Shifters Output Switches SW0 DIN CLK D LE CL SW1 16-Bit Shift Register D LE CL SW2 DOUT D LE CL SW14 D LE CL SW15 VDD GND LE CL VNN VPP RGND HV2701 Ordering Information Package Options DEVICE 48-Lead LQFP (FG) (7x7x1.4mm body, 0.50mm pitch) Pin Configuration 48 1 HV2701 -G indicates package is RoHS compliant (`Green') HV2701FG-G Absolute Maximum Ratings Parameter VDD Logic supply VPP-VNN differential supply VPP Positive supply VNN Negative supply Logic input voltage Analog signal range Peak analog signal current/channel Storage temperature Power dissipation Value -0.5V to +7V 220V -0.5V to VNN+200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP 3.0A -65C to 150C 1.0W 48-Lead LQFP Package (FG) (top view) Product Marking Top Marking YYWW HV2701FG LLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging *May be part of top marking Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 48-Lead LQFP Package (FG) Recommended Operation Conditions Symbol VDD VPP VNN VIH VIL VSIG TA Parameter Logic power supply voltage Positive high voltage supply Negative high voltage supply High level input voltage Low level input voltage Analog signal voltage peak-topeak Operating free air temperature Value 3.0V to 5.5V +40V to VNN +200V -40V to -160V 0.9VDD to VDD 0V to 0.1VDD VNN+10V to VPP- 0V 0C to 70C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powereddown last. 2. VSIG must be within VNN and VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 2 HV2701 DC Electrical Characteristics (over recommended operating conditions unless otherwise noted) 0C Sym Parameter Min RONS Small signal switch on-resistance RONS RONL RINT ISOL VOS IPPQ INNQ IPPQ INNQ ISW fSW Small signal switch on-resistance matching Large signal switch on-resistance Value of output bleed resistor Switch off leakage per switch* DC offset switch off* DC offset switch on* Quiescent VPP supply current Quiescent VNN supply current Quiescent VPP supply current Quiescent VNN supply current Switch output peak current Output switching frequency Max 30 25 25 18 23 22 20 Min Typ 26 22 22 18 20 16 5.0 Max 38 27 27 24 25 25 20 Min Max 48 32 30 27 30 27 20 % ISIG = 5.0mA ISIG = 200mA ISIG = 5.0mA ISIG = 200mA ISIG = 5.0mA ISIG = 200mA VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V +25C +70C Units Conditions ISIG = 5.0mA, VPP = +100V, VNN = -100V VSIG= VPP -10V, ISIG = 1.0A Output Switch to RGND IRINT = 0.5mA VSIG = VPP -10V and VNN +10V No Load All switches off All switches off All switches on, ISW = 5.0mA All switches on, ISW = 5.0mA VSIG duty cycle < 0.1% Duty cycle = 50% VPP = +40V VNN = -160V - - - 15 - - - - - 20 35 50 - - K - 5.0 300 500 3.0 6.5 4.0 4.0 6.5 4.0 4.0 4.0 10 10 0.45 0.45 - 1.0 100 100 10 -10 10 -10 3.0 0.70 0.70 - 10 300 500 50 -50 50 -50 2.0 50 7.0 5.5 5.0 7.0 5.0 5.0 4.0 10 10 0.40 0.40 - 15 300 500 2.0 8.0 5.5 5.5 8.0 5.5 5.5 4.0 10 10 A mV mV A A A A A kHz IPP Average VPP supply current - mA VPP = +100V VNN = -100V VPP = +160V VNN = -40V VPP = +40V VNN = -160V INN Average VNN supply current - mA VPP = +100V VNN = -100V VPP = +160V VNN= -40V All output switches are turning On and Off at 50KHz with no load. IDD IDDQ ISOR ISINK CIN Average VDD supply current Quiescent VDD supply current Data out source current Data out sink current Logic input capacitance 0.45 0.45 - mA A mA mA pF fCLK = 5.0MHz, VDD = 5.0V All logic inputs are static VOUT = VDD-0.7V VOUT = 0.7V --- * See Test Circuits on page 5 3 HV2701 AC Electrical Characteristics (over recommended operating conditions, VDD= 5.0V, tR = tF 5.0ns, 50% duty cycle, CLOAD = 20pF, unless otherwise noted) Sym tSD tWLE Parameter Set up time before LE rises Time width of LE 0C Min 25 56 12 50 15 55 21 7 2 dv/dt Maximum VSIG slew rate KO KCR IID CSG(OFF) CSG(ON) +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK Output voltage spike* Off isolation* Switch crosstalk* Output switch isolation diode current Off capacitance SW to GND On capacitance SW to GND -30 -58 -60 5.0 25 Max 100 40 8 20 50 5.0 5.0 20 20 20 300 17 50 Min 25 50 15 55 2 -30 -58 -60 5.0 25 +25C Typ 56 12 78 30 21 7 -33 -70 12 38 Max 100 40 8 20 50 5.0 5.0 20 20 20 300 17 50 150 +70C Min 25 56 12 50 15 55 21 7 2 -30 -58 -60 5.0 25 Max 100 40 8 20 50 5.0 5.0 20 20 20 300 17 50 dB dB mA pF pF v/ns MHz ns s s Units ns ns Conditions --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD= 5.0V --VDD= 3.0V VDD= 5.0V VDD= 3.0 or 5.0V VDD= 3.0V VDD= 5.0V ---VSIG = VPP-10V, RLOAD = 10K VSIG = VPP-10V, RLOAD = 10K VPP = +40V, VNN = -160V VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V f = 5.0MHz, 1K//15pF load f = 5.0MHz, 50 load f = 5.0MHz, 50 load 300ns pulse width, 2.0% duty cycle 0V, f = 1.0MHz 0V, f = 1.0MHz VPP = +40V, VNN = -160V, RLOAD = 50 mV VPP = +100V, VNN = -100V, RLOAD = 50 VPP = +160V, VNN = -40V, RLOAD = 50 VPP= +40V, VNN= -160V, VSIG= 0V pC VPP= +100V, VNN= -100V, VSIG= 0V VPP= +160V, VNN= -40V, VSIG= 0V tDO tWCL tSU tH fCLK tR,tF TON TOFF Clock delay time to data out Time width of CL Set up time data to clock Hold time data from clock Clock frequency Clock rise and fall times Turn ON time* Turn OFF time* ns ns ns ns - - - - 150 - - - - - - 150 - - - - - 820 - - - QC Charge injection* - - - 600 - - - - - - 350 - - - * See Test Circuits on page 5 4 HV2701 HV2701 Test Circuits VPP-10V VPP-10V Open RGND RGND RGND PP PP DD PP PP DD PP PP DD Switch Off Leakage per Switch DC Offset Switch ON/OFF TURN (TON/TOFF) ON/OFF TIME RGND RGND PP PP PP DD PP DD PP PP DD RGND OFF Isolation Output Switch Isolation Diode Current Switch Crosstalk RGND RGND PP PP PP DD PP DD Q = 1000pF x VOUT Charge Injection Output Voltage Spike 5 HV2701 Logic Function Table D0 L H X X Notes: 1. 2. 3. 4. 5. 6. D1 L H X X ... D7 L H - D8 L H X X ... D15 L H LE L L L L L L L L L L L L L L L L H X CL L L L L L L L L L L L L L L L L L H SW0 OFF ON - SW1 OFF ON - ... SW7 OFF ON - SW8 OFF ON - ... SW15 OFF ON ... ... ... ... X X X X X X X X HOLD PREVIOUS STATE ALL SWITCHES OFF The 16 switches operate independently. Serial data is clocked in on the L to H transition of the CLK. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. DOUT is high when data in the shift register 15 is high. Shift registers clocking has no effect on the switch states if LE is high. The CL clear input overrides all other inputs. Logic Timing Waveforms DN+1 DATA IN 5 0% DN 50% DN -1 LE 50% 50% t WLE t SD 50% 50% th t DO CLOCK t SU DATA O UT 50% t OFF t ON V OUT (TYP ) OFF ON 90% 1 0% CLR 5 0% t WCL 5 0% 6 HV2701 Pin Configuration 48-Lead LQFP (FG) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 Function NC NC SW4B SW4A SW3B SW3A SW2B SW2A SW1B SW1A SW0B SW0A Pin # 13 14 15 16 17 18 19 20 21 22 23 24 Function VNN NC VPP NC GND VDD DIN CLK LE CLR DOUT RGND Pin # 25 26 27 28 29 30 31 32 33 34 35 36 Function SW15B SW15A SW14B SW14A SW13B SW13A SW12B SW12A SW11B SW11A NC NC Pin # 37 38 39 40 41 42 43 44 45 46 47 48 Function SW10B SW10A SW9B SW9A SW8B SW8A SW7B SW7A SW6B SW6A SW5B SW5A NC = No Internal Connection 7 HV2701 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.4mm height (min), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane Top View View B A A2 Seating Plane A1 View B Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX Drawings not to scale. A 1.40 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 D 8.80 9.00 9.20 D1 6.80 7.00 7.20 E 8.80 9.00 9.20 E1 6.80 7.00 7.20 e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC 0O 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2701 B060707 8 |
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